1. Field of the Invention
Embodiments of the invention relate to various systems and methods related to semiconductor memory devices. More particularly, embodiments of the invention relate to non-volatile semiconductor memory devices having a fast continuous burst read mode capability.
This application claims priority under 35 U.S.C § 119 to Korean Patent Application 2005-131859 filed on Dec. 28, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
High speed, high density flash memories are increasingly favored for use in mobile systems. Two forms of prominent flash memories include the NAND-type flash memory in which memory cells are serially connected to a bit line, and the NOR-type flash memory in which memory cells are connected in parallel to a bit line. The NOR-type flash memory has a faster access speed than the NAND-type flash memory, which makes the NOR-type flash memory more competitive for use with high-frequency memory systems. However, because of its larger current consumption, the NOR-type flash memory has a relative disadvantage with respect to high density integration.
A cell array of a NOR-type flash memory includes a plurality of banks, each of which has a plurality of sectors with each sector having a plurality of memory cells. In general, erase operations of NOR-type flash memories are executed by sector units and program operations are executed by a byte or word unit.
In order to program data to a cell array of a NOR-type flash memory, a program command and a program address can be input to the memory, which causes a program voltage to be applied to the appropriate selected bit lines that physically executes the program operation. After program execution, a “program verify” operation can be executed to verify whether the desired program data was stored in the selected memory cells. The program and verify operations can be iteratively executed until all of the desired data all is programmed to the selected memory cells.
In advance of a program operation, the memory block corresponding to the program address may be erased, i.e., each memory cell is set to a [1] for a Single Level Cell (SLC) device or a [11] for a Multi-Level Cell (MLC) device. If program data is a [1] (SLC) or a [11] (MLC), no program voltage is applied to a corresponding bit line as the preservation of an erased state has the same effect as the programming of [1](SLC) or [11](MLC) data to the selected memory cell.
Considering the program characteristics of NOR-type flash memories, it is more time effective to scan incoming data bits for non-erased states, e.g., [0] or [01], and program only the non-erased states, than to simply program all incoming bits. To further increase program speed, the above-mentioned scanning and programming procedures may be performed simultaneously using a programming scheme referred to as a “Pipelined Buffer Program scheme”
Referring to FIG. 1, a conventional semiconductor memory device supporting a pipelined buffer program scheme will be described. As shown in FIG. 1, the conventional semiconductor memory device includes a cell array 10, a sense amplifier and write driver block 20, a data buffer block 30, a bit scanning block 40, a write driver latch block 50 and control logic 60. The control logic 60 controls the pipelined-buffer program operation described below.
To program the cell array 10, N-word program data is loaded on the data buffer block 30 in 4N-word data units. Next, the bit scanning block 40 receives the N-word data from the data buffer block 30 and sequentially stores the N-word data in an internal scan latch circuit 41. Then, the bit scanning block 40 can scan the N-word data stored in the scan latch 41 to select those data bits with a non-erased state. Subsequently, the write driver latch block 50 can receive the scanned data bits from the bit scanning block 40 and provide them to the sense amplifier and write driver block 20.
Once the scanned data bits are received by the sense amplifier and write driver block 20, the sense amplifier and write driver block 20 can apply a program voltage to bit lines corresponding to the received scanned data bits, and programming and scanning of the scanned data bits can be executed simultaneously. The concurrent programming and scanning operations enables a program speed of the NOR-type flash memory to be improved.
FIG. 2 shows the flow of a data programming procedure for a memory device, such as the memory device illustrated in FIG. 1. Referring to FIG. 2, a sense amplifier and write driver block 20 includes a write driver circuit 21 and a sense amplifier circuit 22. The write driver circuit 21 includes multiple write drivers (not shown), and the sense amplifier circuit 22 includes multiple sense amplifiers (also not shown). The number of write drivers in the write driver circuit 21 is the same as the number of sense amplifiers in the sense amplifier circuit 22. Hereinafter, the number of write drivers is referred to as a “write driver size”, and the number of sense amplifiers is referred to as a “sense amplifier size”. Accordingly, the write driver size of the write driver circuit 21 is the same as the sense amplifier size of the sense amplifier circuit 22. The numbers of latches and buffers in the data buffer block 130, the bit scanning block 140, and the write driver latch block 150 are determined on the sense amplifier size and the write driver size.
It should be appreciated that systems that adopted the above-mentioned memory devices are gradually using ever-higher higher clock frequencies and larger storage capacities. To satisfy this demand, the incorporated memory devices are required to have more memory cells and more sense amplifiers per bank. However, these needs result in various disadvantages. For example, the increase of sense amplifiers leads to an increase in latches, e.g., latches in the scan latch circuit 41 and the driver latch block 50. This in turn leads to an increase in chip size. Additionally, the increase of sense amplifiers leads to the increase of main data lines (MDLs), which leads to an increase in layout area/chip size. Further, during a read-while-write (RWW) operation, the increase of sense amplifiers causes verify sensing noise, which can affect a read operation of another bank.
Accordingly, it is desirable to prevent the above drawbacks caused when the number of sense amplifiers and write drivers are increased to realize high-speed and high-density NOR-type flash memories.